1. Field of the Invention
The present invention relates to a semiconductor integrated circuit (LSI). More particularly, the invention relates to a semiconductor integrated circuit equipped with an input circuit or an output circuit adapted to an interchip input/output interface on a board mounting a plurality of LSI chips, and particularly equipped with an input circuit that can be adapted to both the data that operate with high-frequency clocks (e.g., 50 MHz or higher) (hereinafter referred to as high-speed data) and the data that operate with low-frequency clocks (e.g., 50 MHz or lower)(hereinafter referred to as low-speed data) or equipped with an output circuit that outputs very small-amplitude signals of the CTT (center tapped termination) level or the GTL (gunning transceiver logic) level.
2. Description of the Related Art
So far, the TTL or CMOS level, or the LVTTL (interface specification for 3.3 volt power supply standardized in compliance with JEDEC) has generally been used as the input/output level of the LSIs. With respect to these levels, however, the device is much affected by the reflection of signals or by the crosstalk as the frequency of the transfer data exceeds 50 MHz, and it becomes difficult to normally transfer the data since the waveforms are distorted by ringing and the like. Attention therefore has been given to input/output interfaces (CTT, GTL, rambus channel, etc.) of small amplitudes that suppress the amplitude of the transfer data to be smaller than 1 volt (about xc2x1300 to xc2x1500 Mv). These input/output interfaces make it possible to transfer the data at speeds as high as 100 MHz or more, which is well greater than 50 MHz.
However, conventional semiconductor integrated circuits equipped with such input/output interfaces involve many problems, which will be explained later in detail in contrast with the preferred embodiments of the present invention.
A main object of the present invention is to provide a semiconductor integrated circuit equipped with an input circuit or an output circuit adapted for an input/output interface suitable for a small-amplitude operation.
A first object of the present invention is to provide a semiconductor integrated circuit equipped with an input circuit that can be adapted for both the high-speed transfer (importance is placed on the transfer speed) and the low-speed transfer (importance is placed on the electric power efficiency.)
A second object of the present invention is to provide a semiconductor integrated circuit which exhibits performance adapted for various modes and excellent compatibility, by using two sets of output transistors having optimum internal resistances depending upon the signal interfaces (CTT or GTL) of very small amplitude levels and the signal interfaces (CMOS or TTL) of large amplitudes.
A third object of the present invention is to provide a semiconductor integrated circuit which is immune to noise and can be well combined with a three-state type output circuit, by optimizing the judgement reference level of a differential amplifier circuit.
A fourth object of the present invention is to provide a semiconductor integrated circuit equipped with an output circuit having excellent compatibility which can be used for every one of CTT, TTL and GTL.
A fifth object of the present invention is to provide a semiconductor integrated circuit which can be used for both the signal interface having a large logic amplitude and the signal interface having a small logic amplitude.
A sixth object of the present invention is to provide a semiconductor integrated circuit equipped with an output circuit which can realize a high-speed operation and enhance the drivability of output transistors.
According to a first aspect of the present invention, there is provided a semiconductor integrated circuit comprising a switching means which controls the supply of power-source voltage to a signal amplifier circuit that receives input signals, and a control means which selectively turns the switching means on and off depending upon the amplitude or the frequency of the input signals.
According to a second aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a pair of differential transistors which apply to one control electrode an input signal that changes with a first frequency or with a second frequency lower than the first frequency and apply to the other control electrode a reference voltage that corresponds nearly to an intermediate value of the logic amplitude of the input signal; a transistor of the low-potential side disposed between said pair of differential transistors and a power source of the low-potential side; a transistor of the high-potential side disposed between the differential transistors and an active load or between the active load and a power source of the high-potential side; a first control voltage-generating means for generating a control voltage which renders both the low-potential the transistor and said high-potential side transistor conductive when the frequency of the input signal is near the first frequency; and a second control voltage-generating means for generating a control voltage which renders either the low-potential side transistor or the high-potential side transistor conductive depending upon the logic state of the input signal when the frequency of the input signal is near the second frequency.
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit comprising a comparator circuit which detects the magnitude of an input voltage with respect to a voltage that serves as a reference, and an input circuit in which first and second transistors that control the power source current to the comparator circuit are connected between first and second power sources and the comparator circuit, and an input signal fed to the comparator circuit is also fed to the first and second transistors.
According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a pair of differential transistors which apply to one control electrode an input signal which has a first logic amplitude or a second logic amplitude greater than the first logic amplitude and apply to the other control electrode a reference voltage that corresponds nearly to an intermediate value of the logic amplitude of the input signal; a transistor of the low-potential side disposed between the pair of differential transistors and a power source of the low-potential side; a transistor of the high-potential side disposed between the differential transistors and an active load or between the active load and a power source of the high-potential side; and wherein the input signal is applied to the control electrodes of the low-potential side transistor and of the high-potential side transistor.
According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a transmission line for transmitting input signals; a voltage source for generating a voltage that corresponds nearly to an intermediate value of the logic amplitude of the input signal; a terminal resistor which is connected between the transmission line and the voltage source via a predetermined switching means; and an on/off control means which turns the switching means on when the frequency of the input signal corresponds to the first frequency and turns switching means off when the frequency of the input signal corresponds to the second frequency.
According to a sixth aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a first PMOS transistor and a first NMOS transistor connected in series between a high-potential side power source and a low-potential side power source; a second PMOS transistor and a second NMOS transistor connected in series between the high-potential side power source and the low-potential side power source; and an on/off control means which selectively turns the four transistors on and off depending upon a signal logic from a circuit in the chip; wherein a point at which the first PMOS transistor and the first NMOS transistor are connected together and a point at which the second PMOS transistor and the second NMOS transistor are connected together, are both connected to a signal line outside the chip, and the signal line is connected to the high-potential side power source or to the low-potential side power source depending upon the selective on/off operations of the four transistors; the semiconductor integrated circuit further comprising a mode control means which permits the signal line to be driven by the first PMOS transistor or by the first NMOS transistor when a mode designation signal indicates a first transfer mode which is used by connecting a terminal resistor between the signal line and a predetermined constant voltage, and permits said signal line to be driven by the second PMOS transistor or by the second NMOS transistor when the mode designation signal indicates a second transfer mode that is used without connecting the terminal resistor; and, wherein on-resistances of the first PMOS transistor and the first NMOS transistor are set based upon the signal amplitude on the signal line during said first transfer mode and the value of the terminal resistor, and on-resistances or the second PMOS transistor and the second NMOS transistor are set based upon the signal amplitude on the signal line during the second transfer mode.
According to a seventh aspect of the present invention, there is provided a semiconductor integrated circuit comprising differential transistors that output a signal corresponding to a difference between an input signal of a very small amplitude and a reference potential that corresponds to an intermediate amplitude of the signal, the differential transistors having different threshold values.
According to an eighth aspect of the present invention, there is provided a semiconductor integrated circuit equipped with an output circuit comprising: a PMOS transistor and an NMOS transistor connected in series between a high-potential side power source and a low-potential side power source; an output terminal drawn from a point at which the two transistors are connected together; a first means for push-pull operating PMOS transistor and the NMOS transistor according to the logic of a signal that is to be output; and a second means for cutting the PMOS transistor off in response to a predetermined level designation signal.
According to a ninth aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a differential gate which compares the potential of an input signal with a predetermined reference potential to discriminate the logic of the input signal; a selection means which selects either a first reference potential given from outside the chip or a second reference potential formed by a reference potential-generating means in the chip; and an instruction means which instructs the selection means to select the first reference potential when the first reference potential is given, and which instructs the selection means to select the second reference potential when the first reference potential is not given.
According to a tenth aspect of the present invention, there is provided a semiconductor integrated circuit comprising: a logic gate which compares an input signal with a predetermined input threshold value to discriminate the logic of the input signal; a differential gate which compares the potential of the input signal with a reference potential given from outside the chip to discriminate the logic of the input signal; a selection means which selects either the output of the logic gate or the output of the differential gate; and an instruction means which instructs the selection means to select the output of the differential gate when the reference potential is given, and which instructs the selection means to select the output of the logic gate when the reference potential is not given.
According to an eleventh aspect of the present invention, there is provided a semiconductor integrated circuit comprising: an output circuit which outputs a first output voltage that specifies an xe2x80x9cHxe2x80x9d level and a second output voltage that specifies an xe2x80x9cLxe2x80x9d level with respect to a predetermined reference voltage; and a control means which controls the first and second output voltages of under substantially no-load state to, respectively, possess predetermined voltage levels of absolute values which is smaller than the absolute value of the voltage which corresponds to the power-source voltage.